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TTP224B 15/06/16 page 1 of 11 version 1.1 4 keys touch pad detector ic outline z the TTP224B tontouch tm ic is capacitive sensing design s pecifically for touch pad controls. the device built in regulator for touch sensor. stable sensing method can cover diversity conditions. human interfaces control panel li nks through non-conductive dielectric material. the main application is focused at replacing of the mechanical switch or button. the assp can independently handle the 4 touch pads with 4 direct output pins characteristic z operating voltage 2.4v ~ 5.5v z built-in regulator with external enable/disable option (regen pin) z operating current, @vdd=3v no load at low power mode typical 2.5ua, at fast mode typical 13ua z @vdd=3v operating voltage : the response time about 160ms at low power mode, 60ms at fast mode z sensitivity can adjust by the capacitance 1~50pf outside for each touch pad z provides fast mode and low power mode selection by pad option (lpmb pin) z provides direct mode or toggle mode cmos output or open drain output active high or active low by pad option (tog/od/ahlb pin) z have the maximum on time 120sec/64sec/16sec/infinite by pad option(mot1, mot0 pin) z provides single-key and multi-key functions by pad option (sm pin) z after power-on have about 0.5sec stable-time, during the time do not touch the key pad, and the function is disabled z auto calibration for life z the re-calibration period is about 1 sec within 8 sec after power-on. when key has been touched within 8 sec or key has not been touched more than 8 sec after power-on, then the re-calibration period change to 4 sec applications z wide consumer products z button key replacement
TTP224B 15/06/16 page 2 of 11 version 1.1 block diagram pin description pad no pad name type pad description 1 tp0 i/o touch pad input pin 2 tp1 i/o touch pad input pin 3 tp2 i/o touch pad input pin 4 tp3 i/o touch pad input pin 5 ahlb i-pl output active high or low option, default: 0 6 vdd p positive power supply 7 vreg p internal regulator output pin 8 tog i-pl output type option, default: 0 9 lpmb i-pl low power/fast mode option, default: 0 10 mot1 i-ph 11 mot0 i-ph key maximum on time option, default: 1 12 vss p negative power supply, ground 13 regen i-ph internal regulator enable/disable function option, default: 1 14 od i-ph output open-drain option, default: 1 15 sm i-ph single/multi key option, default: 1 16 tpq3 o direct output for tp3 touch input pin 17 tpq2 o direct output for tp2 touch input pin 18 tpq1 o direct output for tp1 touch input pin 19 tpq0 o direct output for tp0 touch input pin pin type z i cmos input only z i-ph cmos input and pull-high resister z o cmos push-pull output z i-pl cmos input and pull-low resister z i o cmos i o z od open drain output, have no diode p rotective circuit z p power ground regen mot1 mot0 lpmb control circuit function option timing counter & tog control key-on & timing circuit system oscillator vreg regulator circuit sm ahlb od tp0 tp3 tp2 tp1 tpq3 tpq2 tpq1 tpq0 circuit sensor oscillator circuit touch detecting detecting circuit reference sensor & circuit driver & mode output
TTP224B 15/06/16 page 3 of 11 version 1.1 pad?s diagram chip size: 1165um x 1165um substrate floating (recommend) or vss pad?s coordinate pad no. pad name x y 1 tp0 47.850 482.950 2 tp1 -57.150 482.950 3 tp2 -485.000 423.850 4 tp3 -485.000 318.850 5 ahlb -485.000 213.850 6 vdd -76.450 -485.000 7 vreg 28.550 -485.000 8 tog 133.550 -485.000 9 lpmb 238.550 -485.000 10 mot1 343.550 -485.000 11 mot0 448.550 -485.000 12 vss 485.000 -263.250 13 regen 485.000 -117.600 14 od 485.000 -7.600 15 sm 485.000 102.400 16 tpq3 485.000 212.400 17 tpq2 485.000 322.400 18 tpq1 257.850 482.950 19 tpq0 152.850 482.950
TTP224B 15/06/16 page 4 of 11 version 1.1 electrical characteristics z absolute maximum ratings z dc / ac characteristics test condition at room temperature = 25 parameter symbol conditions rating unit operating temperature t op -40 +85 storage temperature t stg -50 +125 supply voltage vdd ta=25 c vss-0.3 vss+5.5 v input voltage v in ta=25 c vss-0.3 vdd+0.3 v human body mode esd 5 kv note vss symbolizes for system ground parameter symbol test condition min typ max unit internal regulator disable 2.0 5.5 v operating voltage vdd internal regulator enable 2.4 5.5 v internal regulator output vreg 2.2 2.3 2.4 v i opl vdd=3v, at low power mode(regulator enable) 2.5 ua operating current i opf vdd=3v, at fast mode (regulator enable) 13.0 ua input ports v il input low voltage 0 0.2 vdd input ports v ih input high voltage 0.8 1.0 vdd output port sink current i ol vdd=3v, v ol =0.6v 8 ma output port source current i oh vdd=3v, v oh =2.4v -4 ma input pin pull-high resistor r ph vdd=3v 30k ohm input pin pull-low resistor r pl vdd=3v 25k ohm vdd=3v at fast mode 60 output response time t r vdd=3v at low power mode 160 ms
TTP224B 15/06/16 page 5 of 11 version 1.1 function description . sensitivity adjustment the total loading of electrode size and capacitance of connecting line on pcb can affect the sensitivity. so the sensitivity adjustment must according to the practical application on pcb. the TTP224B offers some methods for adjusting the sensitivity outside 1. by the electrode size under other conditions are fixed. using a lar ger electrode size can increase sensitivity. otherwise it can decrease sensitivity. but the electrode size must use in the effective scope 2. by the panel thickness under other conditions are fixed. using a thinner panel can increase sensitivity. otherwise it can decrease sensitivity. but the panel thickness must be below the maximum value 3. by the value of cs0~cs3 please see the down figure under other conditions are fixed. add the capacitors cs0~cs3 can fine tune the sensitivity for single key, that lets all ke y?s sensitivity identical. when do not use any capacitor to vss, the sensitivity is most sensitive. when adding the values of cs0~cs3 will reduce sensitivity in the useful range 1 Q cs0~cs3 Q 50pf mot1 mot0 regen sm od tog lpmb ahlb vss vreg tpq0 tpq3 tpq2 tpq1 cs3 cs2 cs1 cs0 electrode k3 k0 k1 k2 tp3 tp2 tp1 vdd vdd tp0
TTP224B 15/06/16 page 6 of 11 version 1.1 . output mode by tog od ahlb pad option the TTP224B outputs tpq0~tpq3 has direct mode active high or low by ahlb pad option, has toggle mode by tog pad option and has open drain(have diode protective circuit) mode by od pad option tog od ahlb pad tpq0 tpq3 option features remark 0 1 0 direct mode, cmos output active high default 0 1 1 direct mode, cmos output active low 0 0 0 direct mode, open drain output active high 0 0 1 direct mode, open drain output active low 1 1 0 toggle mode, cmos output, power on state=0 1 1 1 toggle mode, cmos output, power on state=1 1 0 0 toggle mode, power on state high-z, active high 1 0 1 toggle mode, power on state high-z, active low . key operating mode by sm pad option the TTP224B has the single-key and multi-key functions by sm pad option sm option features remark 1 multi-key mode default 0 single key mode multi-key mode the tp0-tp3 can be detected 2 keys or above 2 keys at the same time single-key mode the tp0-tp3 can be detected 1 key only at the same time, when any key be detected, the other 3 keys can not be detected
TTP224B 15/06/16 page 7 of 11 version 1.1 . maximum key on duration time by mot1 mot0 pad option if some objects cover in the sense pad, and causing the change quantity enough to be detected. to prevent this, the TTP224B sets a timer to monitor the detection. the timer is the maximum on duration time. when the detection is over the timer, the system will return to the power-on initial state, and the output becomes inactive until the next detection mot1 mot0 option features remark 0 0 maximum on time 120 sec 0 1 maximum on time 64 sec 1 0 maximum on time 16 sec 1 1 infinite disable maximum on time default . fast and low power mode select by lpmb pad option the TTP224B has fast mode and low power mode to be selected. it depends on the state of lpmb pad. when the lpmb pin is connected to vdd, the TTP224B runs in fast mode. when the lpmb pin is opened or connected to vss, the TTP224B runs in low power mode. in the fast mode response time is faster, but the current consumption will be increased. in the low power mode it will be saving power, but will be slowing response time for first touch. when it awaked in fast mode, the response time is the same the fast mode. in this mode when detecting key touch, it will switch to fast mode. until the key touch is released and will keep a time about 8sec. then it returns to low power mode. the states and timing of two modes please see below figure. low power mode timing diagram: fast mode timing diagram:
TTP224B 15/06/16 page 8 of 11 version 1.1 lpmb option features remark 1 fast mode 0 low power mode default . internal regulator enable/disable the TTP224B built in regulator in the chip. the regulator can be set enable or disable by the regen pin. the regen pin is opened or connected to vdd, the regulator is enabled. the regen pin is connected to vss, the regulator is disabled. when the internal regulator is disabled, the vreg pin must be connected to external vdd. regen option features remark 1 enable internal regulator default 0 disable internal regulator
TTP224B 15/06/16 page 9 of 11 version 1.1 application circuit 19 18 17 16 15 14 13 12 vss tpq2 od sm tpq3 regen vss fs5 fs4 t0 t1 t2 t3 t4 t5 2 c1 104 mot0 11 mot1 lpmb tog vreg vdd 10 9 8 7 6 fs1 fs2 fs3 ahlb tp2 tp3 5 4 3 tp0 tp1 1 tpq0 tpq1 k0 k1 k2 cs3 k3 cs0 cs1 cs2 option table: low power mode option features infinite(disable maximum on time) maximum on time 16sec maximum on time 64sec option features maximum on time 120sec single key mode multi-key mode option features open fast mode vdd fast and low power mode: lpmb open open vss vss open open vss vss mot0 mot1 sm open maximum key on duration time: vss key operation mode: option features open regen internal regulator disable internal regulator enable internal regulator enable/disable: vss tog toggle mode, power on state high-z, active low toggle mode, cmos output, power on state =1 toggle mode, power on state high-z, active high toggle mode, cmos output, power on state =0 open open open vdd vdd vdd vdd vdd vss vss vss open open open vss vdd vdd open open open open vdd open open direct mode, open drain active low output direct mode, open drain active high output direct mode, cmos active low output direct mode, cmos active high output od ahlb pad tpq0~tp3 option features output mode: p. s . 1. on pcb, the length of lines from t ouch pad to ic pin shorter is better. and the lines do not parallel and cross with other lines. 2. the power supply must be stable. if the supply voltage drift or shift quickly, maybe causing sensitivity anomalies or false detections. 3. the material of panel covering on the pcb can not include the metal or the electric element. the paints on the surfaces are the same. 4. the c1 capacitor must be used between v dd and vss; and should be ro uted with very short tracks to the device?s vdd and vss pins (TTP224B). 5. the capacitance cs0~cs3 can be used to adjus t the sensitivity. the value of cs0~cs3 use smaller, then the sensitivity will be better. the sensitivity adjustment must according to the practical application on pcb. the range of cs0~cs3 value are 1~50pf. 6. the sensitivity adjustment capacitors cs0~cs3 must use smaller temperature coefficient and more stable capacitors. such are x7r, npo for ex ample. so for touch application, recommend to use npo capacitor, for reducing that the te mperature varies to affect sensitivity.
TTP224B 15/06/16 page 10 of 11 version 1.1 package outline package type: ssop-20
TTP224B 15/06/16 page 11 of 11 version 1.1 package configuration TTP224B-asd package type ssop-20 tpq0 tpq1 tpq2 tpq3 sm od regen mot0 mot1 tog vreg lpmb 20 19 18 17 16 15 14 13 12 11 10 9 vss 8 7 tp2 tp1 tp0 3 2 1 vdd ahlb tp3 6 5 4 ordering information TTP224B package type chip type wafer type TTP224B-xxx tcp224b tdp224b

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